Autosar 系列教程：小柴带你学 AutoSar 总目录

# 小柴带你学 AutoSar 系列一、基础知识篇（6）车规级 MCU 入门 RH850

# 缘起

这里呢就要浅浅的说一下 TH850 了

当初看手册的时候真的惊呆我啦

6679 页🤯？

这得看到猴年马月啊

然后就打了退堂鼓

哈哈哈哈

今天呢咱就把这 6000 页的文档大概梳理一下。

知识呢学不完，根本学不完🤑！

所以能快速的从自己的知识库中检索知识才是必修课吧😎！

# RH850

RH850 系列芯片是由瑞萨电子（Renesas Electronics）推出的一系列高性能微控制器（MCU），广泛应用于汽车电子领域。

废话不多说啦！建议大家学会看官方手册，帮大家去了解官方手册。

【芯片手册】RH850U2A

我用夸克网盘分享了「RH850U2A.pdf」，点击链接即可保存。打开「夸克 APP」在线查看，支持多种文档格式转换。
链接：https://pan.quark.cn/s/4c76d126966d
提取码：CrVy

【内核手册】RH850G4MH

我用夸克网盘分享了「rh850g4mh.pdf」，点击链接即可保存。打开「夸克 APP」在线查看，支持多种文档格式转换。
链接：https://pan.quark.cn/s/3bdb1ff8f443
提取码：EuAN

# 那我们开始喽

🤩

# 文档目录结构

先来大概了解一下目录，所有的模块基本上都是这个目录

• 模块名称
  • Features③
    • 描述关于具体芯片的特性
  • Overview①
    • 功能的总览介绍
  • Registers④
    • 特别详细的寄存器介绍
  • Operation②
    • 具体的操作流程

熟悉目录结构方便快速查找

# Section 1 Overview

RH850 的特性【这一块的话还是建议大家过一遍的，是整个芯片的功能总览。要实在看不下去就跳过吧哈哈哈】

• CPU0/1/2/3 core

  • RH850G4MH2

• CPU0/1/2/3 instruction cache memory (for Code Flash)

  • 16 KB

• CPU0/1/2/3 data buffer (for Code Flash)

  • 4 lines (256 bit/line)

• Minimum CPU0/1/2/3 instruction execution time

  • 2.5ns (during internal 400 MHz operation)

• General CPU0/1/2/3 registers

  • Thirty-two 32-bit registers

• CPU0/1/2/3 instruction sets

  • Signed multiplication (32 bits × 32 bits → 64 bits): 1 to 2 CPU clocks

  • Saturated operation instructions (with overflow/underflow detection function)

  • 32-bit arithmetic/logical shift instructions: 1 CPU clock

  • Bit manipulation instructions

  • Load/store instructions with long/short formats

  • Signed load instructions

• Inter-Processor Interrupt (IPIR)

  • Support of inter-Processor interrupt function of 4 channels

  • Support level detection of interrupts

  • Accessible from all clusters and all PEs

  • identification of interrupt request source PE is possible.

  • Unintended inter-PE interrupts can be prevented by masking interrupt requests.

  • SET1, CLR1, and NOT1 can be executed as atomic operation instructions to IPIR.

• Barrier-Synchronization (BARR)

  • The 16-ch barrier synchronization registers are provided. Barrier synchronization can be implemented using the same code for all the cores. Accessible from all clusters and all PEs within the systemTime Protection Timer (TPTM) Interval timer × 2ch (down counter), free-run timer × 1ch (up counter), up timer × 2ch (up counter)Start, Stop and Restart of counter for the interval timers, the free-run timer and the up timers.

  • Divided counter of the timers can be configured for the interval timers, the free-run timer, up timer respectively.

  • Simultaneous count control for the interval timers belonging to the same PE.

  • Simultaneous count control for the up timers belonging to the same PE using registers prepared for each PE.

  • Globally simultaneous count control registers are prepared. A PE can control all up counters including ones owned by other PEs.

  • Underflow interrupt for the interval timers.

  • Comparison value matching interrupts for the up timers.

  • Each timer set has 3 control signals to stop timers while in debug mode. One is for interval timers and the free-run timer, another is for up timer 0, the other is for up timer 1.

• Memory space

  • 4-GB address space (common to program and data)

• Code flash

  • Two types of memory area– User area:

    • 16 MB (common to each CPU, ICUMHA) [For U2A-EVA and U2A16 Only]

    • User area: 8 MB (common to each CPU, ICUMHA) [For U2A8 Only]

    • User area: 6 MB (common to each CPU, ICUMHA) [For U2A6 Only]

    • User boot area: 64 KB high-speed reading through cache enabled.

  • OTA (Over-the-Air) update support

• Data flash

  • 512 KB + 64 KB (dedicated to ICUMHA) [For U2A-EVA and U2A16 Only]

  • 256 KB + 64 KB (dedicated to ICUMHA) [For U2A8 Only]

  • 192 KB + 64 KB (dedicated to ICUMHA) [For U2A6 Only]

• RAM

  • Local RAM: 64 KB (CPU0/1/2/3 [For U2A-EVA and U2A16 Only])

  • Local RAM: 64 KB (CPU0/1 [For U2A8 and U2A6 Only])

  • Cluster RAM: 3328 KB (common to each CPU) (256 KB: Retention RAM) [For U2A-EVA and U2A16 Only]

  • Cluster RAM: 1664 KB (common to each CPU) (128 KB: Retention RAM) [For U2A8 Only]

  • Cluster RAM: 640 KB (common to each CPU) (128 KB: Retention RAM) [For U2A6 Only]

  • Cluster Emulation RAM: 2 MB (1 MB for each cluster 0 & 1) [For U2A-EVA Only]

  • Cluster Emulation RAM: 32 KB (cluster 0) [For U2A6 Only]

  • Global Emulation RAM: 2 MB [For U2A-EVA Only]

• Serial Flash Memory I/F (SFMA)

  • 1 unit incorporated [For U2A-EVA, U2A16, U2A8, U2A6 (BGA-292) and U2A6 (QFP-176) Only]One serial Flash Memory device can be connected.

  • A data bus width of 1 bit, 2 bits, or 4 bits can be selected.

  • 4 GB address space

  • Efficient data reception due to built-in read cache (64-bit line × 16 entries)

  • Arbitrary bit rate settable by the on-chip baud rate generator

• Multimedia Card Interface (eMMC)

  • 1 unit incorporated [For U2A-EVA, U2A16, U2A8, U2A6 (BGA-292) and U2A6 (QFP-176) Only]

  • Compliant with JEDEC STANDARD JESD84-A441 (neither DDR mode nor 1.8-V operation is supported).

  • Supports 1-/4-/8-bit MMC bus widths.

  • Supports the backward-compatible mode.

  • High-speed mode is supported.

  • MMC Clock frequency = MMCA module clock frequency/2k (k = 1 to 10).

  • Supports block transfer.

  • Supports boot operation.

  • Supports high priority interrupts (HPI).

  • Supports background operation.

  • Interrupt requests: normal operation and error/timeout.

  • DMA transfer requests: buffer write and buffer read.

• Interrupts/exceptions

  • 1 non-maskable interrupt (NMI pin)

  • 1 FE level interrupt

  • 768 maskable interrupts (high-speed: 32, low-speed: 736)

  • Simultaneous distribution of interrupt sources to multiple cores (each CPU)

  • Applicable sources: non-maskable interrupt (NMI pin), FE level interrupt, 32 high-speed maskable interrupts

  • External interrupt input function (IRQ pins)

  • Software interrupt function (SINT)

  • Inter-processor interrupt function (IPIR)

  • 64-level priority specifiable for maskable interrupts

  • For RH850G4MH2 exceptions, see Section 3.2.4, Exceptions and Interrupts.

• sDMA controller

  • 32 channels incorporated (16 channels × 2 units)

  • Transfer data length: 1 byte, 2 bytes, 4 bytes, 8 bytes, 16 bytes, 32 bytes, 64 bytes

  • Parallel reads and writes (fly-by)

  • Address mode: dual address mode

  • Transfer requests: auto request, peripheral hardware request.

  • Bus modes: normal speed mode, slow speed mode

  • Arbitration modes: fixed priority mode, round-robin modeInterrupt requests: termination of descriptor step, the termination of data transfer, the occurrence of address error.

  • Descriptor memory: 8 KB (shared at all channels).

  • Scatter-gather transfer

  • Transfer target: On-chip memory, on-chip peripheral modules (excluding DTS and sDMAC)

• DTS controller

  • 128 channels incorporated

  • Transfer unit: 8 bits/16 bits/32 bits/64 bits/128 bits64-bit × 2-burst transfer

  • Dual-address transfer mode

  • Address reloading function

  • Chain transfer function

  • Three transfer modes: Single transfer, block transfer 1 (specified by number of transfer times), and block transfer 2 (specified by address count)

  • Transfer target: On-chip memory, on-chip peripheral modules (excluding the DTS and sDMAC)

  • Transfer requests can be set by interrupt sources and the software.

• I/O

  • Output driving ability of specific input/output pins is selectable

  • Inversion or non-inversion of output values of specific input/output pins is selectable

  • Pull-up or pull-down off of specific input/output pins is selectable

• Safety functions

  • Flash memory ECC error detection function

  • RAM ECC error detection function

  • Peripheral module RAM ECC error detection function (e.g. FlexRay, CAN, GTM)

  • Clock monitor

  • Error Control Module (ECM)

  • Duplexing of modules (e.g. CPUs, ECM, error output pins)

  • Automatic Power-on BIST execution after reset

  • Standby Resume BIST (SR-BIST) execution selection after wake-up from DeepSTOP mode.

• Error Control Module (ECM)

  • Collects information for each error check system and safety function and indicates error status.

  • When an error is detected, an error signal can be output from the error pin to the external.

  • Interrupts and internal reset signals can be generated upon detection of an error.

  • Provided with a function to generate a pseudo-error for debugging and self-diagnosis.

• Data CRC Function (KCRC)

  • The data CRC (Cyclic Redundancy Check) function can verify or generate data streams protected by a CRC with various lengths and different bit widths.

• Window Watchdog Timer (WDTB)

  • 5 units incorporated [For U2A-EVA and U2A16 Only]

  • 3 units incorporated [For U2A8 and U2A6 Only]

  • Can generate a signal to the ECM when a counter overflows (timer expires).

  • Can generate an interrupt at 75% of the counter overflow value.

  • An interrupt request can be generated at any function of the counter value.

  • A window open period can be set to any function of the counter value.

• Long-Term System Counter (LTSC)

  • 1 unit incorporated

  • 64-bit counter without overflow.

  • Free-run up counting

  • Atomic read/write access to all registers

  • Anytime read access to counter registers

  • Application reset (SW reset) can be masked. When masked, counter keeps running on reset occurrence and counter register will not be initialized.

• OS Timer (OSTM)

  • 10 units incorporated [For U2A-EVA and U2A16 Only]

  • 8 units incorporated [For U2A8 and U2A6 Only]

  • A 32-bit timer assuming use by OS

  • Interval timer mode or free-running timer mode selectable

  • Synchronous start between units available

• Timer Array Unit D (TAUD)

  • 3 units incorporated

  • The TAUD has the following functions:

    • 16 channels, 16-bit counter and 16-bit data register per channel

    • Independent channel operation

    • Synchronous channel operation (master and slave operation)

    • Generation of different types of output signal

    • Real-time output

    • Counter can be triggered by external signal

    • Interrupt generation

    • The TAUD can operate independently or synchronously (combine with other channels)

• Timer Array Unit J (TAUJ)

  • 4 units incorporated

  • The TAUJ has the following functions:

    • Independent channel operation function (operated using a single channel)

    • Synchronous channel operation function (operated using a master channel and multiple slave channels)

  • The TAUJ can operate independently or synchronously (combine with other channels)

• Motor Control Timer (TSG3)

  • 2 units incorporated [For U2A-EVA, U2A16, U2A8, U2A6 (BGA-292) and U2A6 (QFP-176) Only]

  • 1 unit incorporated [For U2A6 (BGA-156) and U2A6 (QFP-144) Only]

  • 18-bit timer counter

  • Count clock resolution: Minimum 12.5 ns (count clock = 80 MHz)

  • Operating mode corresponding to various motor control methods

  • Compare registers with reload buffer

  • 10-bit dead time counter

  • A/D conversion trigger signal generation

  • Forced output stop function by TAPA

  • Reload (simultaneous rewrite) or anytime rewrite

  • HT-PWM mode with 0-100% duty cycles output

  • Semi-automatic cruise function

  • Three-phase encoder function (hall sensor signals can be input).

  • Fail-safe function (warning interrupt or error interrupt can be generated)

    • Simultaneous active output detect function for positive and inverse phase.

    • Abnormal input detection function of the three-phase encoder

• Timer Option (TAPA)

  • 4 units incorporated [For U2A-EVA, U2A16, U2A8 and U2A6 (BGA-292) Only]

  • 3 units incorporated [For U2A6 (QFP-176) Only]

  • 2 units incorporated [For U2A6 (BGA-156) and U2A6 (QFP-144) Only]

  • Combine with the peripheral interconnect (PIC) to provide the following functions:

    • Asynchronous Hi-Z control function

    • Interrupt signal output function

    • A/D conversion start trigger selection function

• Timer Pattern Buffer (TPBA)

  • 2 units incorporated

  • Count clock resolution: Minimum 12.5 ns (count clock = 80 MHz)

  • 16-bit counte

  • 16-bit duty register

  • 16-bit period setting register

  • 7-bit address counter register

  • 7-bit pattern number setting register

  • Interrupt request signals

    • Period-matched detection interrupt

    • Duty-cycle-matched detection interrupt

    • Number-of-patterns matched detection interrupt

    Number of duty patterns– 64 patterns (16 bits) or 128 patterns (8 bits)

  • Automatic duty generation according to the number of patterns

  • Output control by software

  • The count clock can be selected from PCLK, PCLK/2, PCLK/4, and PCLK/8 according to the prescaler set value.

  • Synchronous start with another timer

• PWM Output/Diagnostic (PWM-Diag)

  • 1 PWBA block for generating clock signals.

  • Generates a count clock signal for PWGC

  • 96 PWGC blocks generate PWM signals. [For U2A-EVA, U2A16, U2A8 and U2A6 (BGA-292) Only]

  • 76 PWGC blocks generate PWM signals. [For U2A6 (QFP-176) Only]

  • 50 PWGC blocks generate PWM signals. [For U2A6 (BGA-156) Only]

  • 64 PWGC blocks generate PWM signals. [For U2A6 (QFP-144) Only]

  • Outputs PWM waveforms and A/D conversion trigger to PWSD

  • 1 PWSD block for generating triggers for A/D conversion.

  • Transmits the required setting information to the A/D converter and outputs the A/D conversion start trigger

• Real-Time Clock (RTCA)

  • 1 unit incorporated

  • Count clock selection from 240 kHz to 2.5 MHz

  • Counters for years, months, day of the month, day of the week, hours, minutes, seconds, and a subcounter.

  • One Hz pulse output function

  • Fixed interval interrupt function

  • Alarm interrupt function

• Peripheral Interconnect function (PIC1)

  • 1 unit incorporated

  • Simultaneous start trigger function

  • INT signal output selection function

  • PWM/Delay pulse output function with dead time

  • Trigger pulse width measurement function

  • Encoder capture trigger select function

  • Two-phase encoder control function

  • Three-phase pulse input control function

  • Three-phase encoder control function

  • TAUD input select function

  • Hi-Z control function

  • Timer output monitor function (PWM-Diag)

  • Timer input monitor function

  • TSG3 Synchronous Clear Function

• Peripheral Interconnect function (PIC2)

  • 3 units incorporated

  • ADCJ trigger select function

  • Signal routing function for GTM:

    • Baud Rate Measurement for an UART (RLIN3)

    • Hi-Z Control Function Over External Pin for GTM Output

    • GTM Output Monitor for PWM Diagnostic

    • ENCA Trigger Selection Function

    • PSI5S Timestamp and the Sync Pulse Signal Selection Function

    • GTM Timer Input (TIM) Selection Function

    • ENCA Encoder Input Selection

• Serial Communication Interface 3 (SCI3)

  • 3 units incorporated [For U2A-EVA, U2A16 and U2A8 Only]

  • Clock synchronization or start-stop system selectable

  • Full-duplex communication enabled

  • Arbitrary bit rate selectable by the on-chip baud rate generator

  • LSB first or MSB first selectable

• Multi-channel Serial Peripheral Interface (MSPI)

  • 10 units incorporated [For U2A-EVA (BGA-516) and U2A16 (BGA-516) Only]

  • 9 units incorporated [For U2A16 (BGA-373) and U2A8 (BGA-373) Only]

  • 6 units incorporated [For U2A16 (BGA-292), U2A8 (BGA-292), U2A6 (BGA-292), U2A6 (QFP-176) and U2A6 (BGA-156) Only]

  • 4 units incorporated [For U2A6 (QFP-144) Only]

  • Chip select: Up to 8 for each unit

  • Three-wire serial synchronous data transfer

  • Master mode or slave mode selectable

  • Settable up to eight channels with phase of clock and data settable

  • Transmission rate up to 40 Mbps

  • Arbitrary bit rate settable by the on-chip baud rate generator

• CANFD interface (RS-CANFD)

  • 16 channels incorporated [For U2A-EVA, U2A16 and U2A8 Only]

  • 12 channels incorporated [For U2A6 (BGA-292) Only]

  • 11 channels incorporated [For U2A6 (QFP-176) Only]

  • 8 channels incorporated [For U2A6 (BGA-156) Only]

  • 7 channels incorporated [For U2A6 (QFP-144) Only]

  • Classical CAN mode (RS-CAN software compatibility mode)

    • Conforming to CAN-FD ISO 11898-1 (2015)

    • Transfer speed up to 1 Mbps

    • A total of 16588 message buffers (Individual 1024 buffers + Shared 15564 buffers when 8 byte data payload) provided for 16 channels [For U2A-EVA, U2A16 and U2A8 Only]

    • A total of 3301 message buffers (Individual 384 buffers + Shared 2917 buffers when 8 byte data payload) provided for 12 channels [For U2A6 (BGA-292) Only]

    • A total of 3026 message buffers (Individual 352 buffers + Shared 2674 buffers when 8 byte data payload) provided for 11 channels [For U2A6 (QFP-176) Only]

    • A total of 2200 message buffers (Individual 256 buffers + Shared 1944 buffers when 8 byte data payload) provided for 8 channels [For U2A6 (BGA-156) Only]

    • A total of 1926 message buffers (Individual 224 buffers + Shared 1702 buffers when 8 byte data payload) provided for 7 channels [For U2A6 (QFP-144) Only]

    • Reception filtering

  • CAN FD mode

    • Conforming to CAN-FD ISO 11898-1 (2015)

    • Transfer speed up to 8 Mbps

    • A total of 5120 message buffers (Individual 1024 buffers + Shared 4096 buffers when 64 byte data payload) provided for 16 channels [For U2A-EVA, U2A16 and U2A8 Only]

    • A total of 1152 message buffers (Individual 384 buffers + Shared 768 buffers when 64 byte data payload) provided for 12 channels [For U2A6 (BGA-292) Only]

    • A total of 1056 message buffers (Individual 352 buffers + Shared 704 buffers when 64 byte data payload) provided for 11 channels [For U2A6 (QFP-176) Only]

    • A total of 768 message buffers (Individual 256 buffers + Shared 512 buffers when 64 byte data payload) provided for 8 channels [For U2A6 (BGA-156) Only]

    • A total of 672 message buffers (Individual 224 buffers + Shared 448 buffers when 64 byte data payload) provided for 7 channels [For U2A6 (QFP-144) Only]

    • Reception filtering

• FlexRay(FLXA)

  • 2 units incorporated [For U2A-EVA, U2A16 and U2A8 Only]

  • 1 unit incorporated [For U2A6 only]

  • Conforming to Protocol Specification v2.1

  • Buffer size: A 8-KB space is divided into up to 128 sections (for transmission, reception, and receive FIFO)

  • Message filtering: slot counter filter, channel filter, cycle counter filter

  • Bit rate: 10 Mbps

• LIN/UART interface (RLIN3)

  • 24 units incorporated [For U2A-EVA (BGA-516), U2A16 (BGA-516), U2A16 (BGA-373) and U2A8 (BGA-373) Only]

  • 12 units incorporated [For U2A16 (BGA-292), U2A8 (BGA-292), U2A6 (BGA-292) and U2A6 (QFP176) Only]

  • 8 units incorporated [For U2A6 (BGA-156) Only]

  • 10 units incorporated [For U2A6 (QFP-144) Only]

  • Conforming to LIN Protocol Spec versions 1.3, 2.0, 2.1, 2.2, and SAE J2602

  • Three operating modes

    • LIN Master mode

    • LIN Slave mode

    • UART mode (half-duplex, full-duplex)

  • Arbitrary bit rate is selectable by the on-chip baud rate generator

  • LIN Self-test mode with internal data loop back

• Clock Extension Peripheral Interface (CXPI)

  • 4 units incorporated [For U2A-EVA, U2A16 and U2A8 Only]

  • Baud rate: 9.6 kbps/10.4 kbps/19.2 kbps/20.0 kbps

  • Master or Slave Mode

  • Event trigger method / Polling method

  • Output and sample the PWM waveform by PWM encoding/decoding function

• I2C Bus Interface (RIIC)

  • 2 units incorporated [For U2A-EVA, U2A16, U2A8, U2A6 (BGA-292), U2A6 (QFP-176) and U2A6 (BGA-156) Only]

  • 1 unit incorporated [For U2A6 (QFP-144) Only]

  • I2C bus format with master mode or slave mode selectable

  • Transfer rate up to 400 kbps

• Single Edge Nibble Transmission (RSENT)

  • 8 units incorporated [For U2A-EVA, U2A16, U2A8, U2A6 (BGA-292), U2A6 (QFP-176) and U2A6 (BGA-156) Only]

  • 6 units incorporated [For U2A6 (QFP-144) Only]

  • Conforming to the SENT (Single Edge Nibble Transmission) protocol specified in the SAE J2716_201604 standard and the SPC (Short PWM Code) extension to the SENT specification

  • Unidirectional or bidirectional transfer is possible through a single pin

  • Bidirectional transfer is possible through two pins

  • Data transfer protected by a CRC is possible

• Peripheral Sensor Interface 5 (PSI5)

  • 4 channels incorporated [For U2A-EVA, U2A16, U2A8, U2A6 (BGA-292), U2A6 (QFP-176) and U2A6 (BGA-156) Only]

  • 3 channels incorporated [For U2A6 (QFP-144) Only]

  • Conformance with PSI5 protocol specification V2.0

  • Bit rates: Low speed(125 kbps), High speed(189 kbps), PAS compatibility mode(250 kbps)

  • Communication Mode selectable

• Peripheral Sensor Interface 5 serial communication module (PSI5S)

  • 2 units incorporated [For U2A-EVA, U2A16, U2A8 and U2A6 (BGA-292) Only]

  • 1 unit incorporated [For U2A6 (QFP-176), U2A6 (BGA-156) and U2A6 (QFP-144) Only]

  • Support the UART based communication for PSI5 transceiver

  • Conformance with PSI5 protocol specification V2.2

  • Generate a PSI5 message from the UART transfer data

  • The bit rate of the UART can be set by the built-in baud rate generator

• RHSIF

  • 1 unit incorporated [For U2A-EVA, U2A16 and U2A8 Only]

  • Asynchronous high speed LVDS interface based on IEEE 1596.3-1996 reduced range link

  • Asynchronous high speed LVDS interface supporting maximum data rates of 320 Mbps

  • Four channels, including one channel with data streaming capability

  • Bus master interface which is used by a target node to access shared memory

• Ethernet Controller(ETNB)

  • 1 channel of 100Mbps ethernet incorporated [For U2A-EVA, U2A16, U2A8, U2A6 (BGA-292), U2A6 (QFP-176) and U2A6 (QFP-144) Only]

  • 1 channel of 1Gbps ethernet incorporated [For U2A-EVA, U2A16 and U2A8 Only]

  • Conformance with the IEEE 802.3 MAC layer standard

  • PHY interface: MII (Media Independent Interface) and RMII (Reduced Media Independent Interface) for 100Mbps; SGMII (Serial Gigabit Media Independent Interface) is for 1Gbps

  • Supports 1Gbps and 100 Mbps or 10 Mbps

  • Supports full-duplex mode

  • built-in DMA transfer function

• Analog to Digital Converter(ADCJ)

  • 94 channels incorporated [For U2A-EVA (BGA-516), U2A16 (BGA-516), U2A16 (BGA-373) and U2A8 (BGA-373) Only]

  • 79 channels incorporated [For U2A16 (BGA-292), U2A8 (BGA-292) and U2A6 (BGA-292) Only]

  • 64 channels incorporated [For U2A6 (QFP-176) Only]

  • 29 channels incorporated [For U2A6 (BGA-156) Only]

  • 39 channels incorporated [For U2A6 (QFP-144) Only]

  • A/D conversion method: Successive approximation

  • Configuration of analog input pins

    • ADCJ0/ADCJ1/ADCJ2 high accuracy inputs: 20/20/20 [For U2A-EVA (BGA-516) and U2A16 (BGA-516), U2A16 (BGA-373) and U2A8 (BGA-373) Only]

    • ADCJ0/ADCJ1/ADCJ2 high accuracy inputs: 20/20/5 [For U2A16 (BGA-292), U2A8 (BGA292) and U2A6 (BGA-292) Only]

    • ADCJ0/ADCJ1/ADCJ2 high accuracy inputs: 14/14/5 [For U2A6 (QFP-176) Only]

    • ADCJ0/ADCJ1/ADCJ2 high accuracy inputs: 8/8/0 [For U2A6 (BGA-156) Only]

    • ADCJ0/ADCJ1/ADCJ2 high accuracy inputs: 10/10/0 [For U2A6 (QFP-144) Only]

    • ADCJ0/ADCJ1/ADCJ2 low accuracy inputs: 10/14/10 [For U2A-EVA, U2A16, U2A8 and U2A6 (BGA-292) Only]

    • ADCJ0/ADCJ1/ADCJ2 low accuracy inputs: 10/14/7 [For U2A6 (QFP-176) Only]

    • ADCJ0/ADCJ1/ADCJ2 low accuracy inputs: 6/7/0 [For U2A6 (BGA-156) Only]

    • ADCJ0/ADCJ1/ADCJ2 low accuracy inputs: 3/10/6 [For U2A6 (QFP-144) Only]

  • Resolution: 12-bit

  • Conversion speed: 1.0 μs

  • Scan groups for five systems for each converter

  • Two scan modes (multicycle scan mode and continuous scan mode)

  • ADCJ0: Up to 64 virtual channels

  • ADCJ1: Up to 64 virtual channels

  • ADCJ2: Up to 64 virtual channels

  • Addition mode A/D conversion functions incorporated

  • Can enter data directly to the Generic Timer Module.

  • Safety functions

  • Supporting an upper / lower-limit-excess-notice-function for the ADC Voltage Monitor Secondary Error Generator in each virtual channel

  • Track & Hold (T&H) input channels

  • 4 channel inputs per unit can select T&H circuit for synchronize conversion.

• Power supply

  • Supports both of 5 V, 3.3 V and 1.09 V power supplies with the exception of the core supply.

  • The power on / off sequence has no constraints.

• Power supply voltage monitor

  • The power supply voltage monitor is used for monitoring power domain E0VCC, VCC, ISOVDD and AWOVDD.

  • The power supply voltage monitor has High-side (HDET) and Low-side (LDET) voltage detectors, which detect if the monitored voltage is more or less than the specified voltage.

  • The power supply voltage monitor have two types detection function of Primary detection and Secondary detection.

  • The Primary detection function is performed by Voltage Monitor. The Secondary detection function is performed by the ADCJ.

  • The Delay Monitor (DMON) assists the VMON which detects the Low-side voltage of ISOVDD.

  • Primary power supply voltage monitor can control on or off for the VMON reset generated by high level/low level detection of ISOVDD, VCC and E0VCC.

  • The Primary detection voltage value is fixed, secondary detection voltage value can be set by the ADCJ.

• Secure Watchdog Timer (SWDT)

  • 1 unit incorporated

  • Can generate an error signal for the Interrupt Controller in response to an error.

  • Confirmation of matching with a specified Program Counter (PC) value of the CPU0.

• Intelligent Cryptographic Unit Master (ICUMHA)

  • The ICUMHA is an on-chip Hardware Security Module (HSM).

  • The ICUMHA supports user-defined security services to the overall system based on cryptographic primitives.

• Debugging and Calibration

  • Nexus JTAG: One channel incorporated

  • LPD (4-pin): One channel incorporated

  • AUDR: One channel incorporated [For U2A-EVA Only]

  • Aurora Trace Interface: One channel incorporated [For U2A-EVA Only]

• Boundary scan

  • Supports boundary scan conforming to the IEEE1149.1 standard

• Clock controller

  • The user is able to select the crystal resonance frequency (16 MHz or 20 MHz or 24 MHz or 40 MHz).

  • Incorporates a crystal resonation circuit (Main OSC), which is used as a reference clock for the PLL.

  • Incorporates High Speed Internal Oscillator (HS IntOSC) and Low Speed Internal Oscillator (LS IntOSC), which are used as the start-up clock and backup clock.

  • Incorporates High Voltage Internal Oscillator (HV IntOSC), which is used as digital noise filter clock for VMON.

  • Incorporates a PLL circuit to generate high speed internal clocks by multiplying the Main OSC input.

  • Generates clock pulses used inside the chip from the internal oscillator, main oscillator and PLL.

  • Software configurable external clock output.

• Operating modes

  • Operating modes

  • Normal Operating Mode

  • User Boot Mode

  • Serial Programming Mode

  • Boundary scan mode

• Standby controller

  • This product supports various power-down modes.

  • The power consumption of the MCU can be reduced by selecting one of the modes:

    • RUN mode

      • RUN mode is a normal operation mode where the CPU is operating and all of other modules can operate. The CPU can enter “HALT” state by executing the “HALT” instruction to stop its operation in this mode.

    • STOP mode

      • STOP mode is a chip-level stand-by mode in which the clock supply to a certain clock domain can be stopped.

    • DeepSTOP mode

      • DeepSTOP mode is a chip-level stand-by mode to reduce power consumption further than STOP mode. In addition to the clock supply stop, the power supply to the Isolated area is switched off.

    • Cyclic RUN mode

      • Cyclic RUN mode is a low-power operation mode in which limited modules can operate at low speed.

    • Cyclic STOP mode

      • Cyclic STOP mode is a STOP mode in cyclic operation, and one CPU halts its operation.

    • Module standby

• Reset controller

  • 7 reset functions

    • Power On Reset

    • System Reset 1

    • System Reset 2

    • Application Reset

    • DeepSTOP Reset

    • Module Reset

    • JTAG Reset

  • External Reset output pin: RESETOUT

  • Automatic RAM initialization after reset (include DTSRAM, sDMAC Descriptor RAM, GTM RAM, MMCA RAM and MSPI RAM).

• Clock monitor

  • Up to 10 clock monitors depending on the device configuration.

  • Detects clock disturbances that results in lower or higher frequency than target frequency, and sends an error notification to the ECM.

  • Supports the self-diagnosis function.

• Low-Power Sampler (LPS)

  • 1 unit incorporated [For U2A-EVA, U2A16, U2A8, U2A6 (BGA-292), U2A6 (QFP-176) and U2A6 (QFP-144) Only]

  • Support checking the digital input ports and analog input ports to monitor the external input without consuming CPU resources.

• Temperature sensor

  • 1 sensor incorporated.

  • Out of range detection of temperature.

  • Operating modes

    • Single measurement mode

    • Continuous measurement mode

  • Interrupt generation

    • Temperature Measurement End Interrupt (INTOTSOTI)

    • Temperature Rise/Drop Interrupt (INTOTSOTULI)

    • Abnormal temperature error signal (OTABE)

    • Temperature Sensor Error (INTOTSOTE)

  • Support self-diagnosis function

• Generic Timer Module (GTM)

  • 1 unit incorporated

  • GTM v3.5 is a modular timer unit and consists of the following submodules.

  • Advanced Routing Unit (ARU)

  • Clock Management Unit (CMU)

  • Cluster Configuration Module (CCM)

  • Time Base Unit (TBU)

  • Timer Input Module (TIM)

  • Advanced Timer Output (ATOM)

  • Dead Time Module (DTM)

  • Multi Channel Sequencer (MCS)

  • Interrupt Concentrator Module (ICM)

  • Output Compare Unit (CMP)

  • Monitoring Unit (MON)

• Encoder Timer (ENCA)

  • 2 units incorporated [For U2A-EVA, U2A16, U2A8 and U2A6 (BGA-292) Only]

  • 1 unit incorporated [For U2A6 (QFP-176) and U2A6 (QFP-144) Only]

  • Generation of the counter control signal from the encoder input signal, and count operation.

  • Capture function for capturing the counter value with an external trigger signal

  • Compare function for compare match judgment with the counter value

  • Two capture compare registers that can be set separately for capture operation and for compare operation

  • Interrupt mask function for masking the interrupt request signal output as a result of the compare match judgment during compare operation

  • Function for loading the value of the capture compare register to the counter upon underflow occurrence

  • The Encoder input signal can be applied to the timer counter clear condition

  • Edge or level can be selected for clearing the encoder input signal of the timer counter clear condition

  • Detection of counter overflow and underflow and output of error flags and error occurrence interrupts

  • Five interrupts: two capture compare interrupts, one counter clear interrupt, one overflow interrupt, and one underflow interrupt.

• Package

  • [For U2A-EVA (BGA-516) and U2A16 (BGA-516) Only]

  • 516-pin plastic FBGA (0.8 mm ball pitch) (25mm × 25mm package size)

  • [For U2A16 (BGA-373) and U2A8 (BGA-373) Only]

  • 373-pin plastic FBGA (0.8 mm ball pitch) (21mm × 21mm package size)

  • [For U2A16 (BGA-292), U2A8 (BGA-292) and U2A6 (BGA-292) Only]

  • 292-pin plastic FBGA (0.8 mm ball pitch) (17mm × 17mm package size)

  • [For U2A6 (QFP-176) Only]

  • 176-pin plastic HLQFP (0.5 mm pin pitch) (24mm × 24mm package size)

  • [For U2A6 (BGA-156) Only]

  • 156-pin plastic FBGA (0.65 mm ball pitch) (10mm × 10mm package size)

  • [For U2A6 (QFP-144) Only]

  • 144-pin plastic HLQFP (0.4 mm pin pitch) (16mm × 16mm package size)

# Section 2 Pin Functions

# 引脚功能设置

​ 页码：P141

​ 描述：设置引脚模式的寄存器说明。这里是索引，将只是串起来。

# ICUM 设置 port 有更高的优先级

# Noise Filter 噪声过滤

# Section 3 CPU System

# 中断等级：EI & FE

# 寄存器组

这块是一些芯片级别的寄存器，操作系统的实现需要用到这些。调试代码的时候也会经常用到，涉及到这块的代码都是通过汇编来写的。汇编的指令可以看官方文档：RH850G4MH 文章开头有下载链接哦！

# psw 说明

页数：P253

# EIIC 表示 EI 中断的原因

中断原因表在这。程序噶了的时候可以追溯原因哦！

页数：P334

# 中断向量表

# 时间戳

寄存器：SR2,11

寄存器名：TSCTRL

描述：可以用来获取时间，做状态机使用（当然 RH850 也有专门的时间模块年月日那种，当然定时器也可以）

代码实现：

void TSCTRL_Init(void){

    __asm("mov r0, r23");

    __asm("add 0x1, r23");

    __asm("ldsr r23, 2, 11");/* set TSCTRL */

}

asm uint32 Os_Hal_GetTSCOUNTL(void){

    stsr 0, r10, 11

}

asm uint32 Os_Hal_GetTSCOUNTH(void){

    stsr 1, r10, 11

}

/* CPU clock 400M , TSCOUNT add 1 on every clock cycle

  Actual time = MCU_Timestamp_Get()/400 us */

uint64 MCU_Timestamp_Get(void){

    uint32 TimeStamp_L = 0u;

    uint32 TimeStamp_H = 0u;

    TimeStamp_L = Os_Hal_GetTSCOUNTL();

    TimeStamp_H = Os_Hal_GetTSCOUNTH();

    return (((uint64)TimeStamp_H << 32) | TimeStamp_L);

}

# 现场保存

描述：操作系统切换上下文时怎么做到的呢？看这里吧

Context Saving

页数：P344

# Section 4 Address Space

描述：地址空间的划分。很重要

• 编译时的链接文件会用到
  • 关于编译请看【小柴带你学 AutoSar 系列一、基础知识篇（4）编译】
• BootLoader 也会用到啦
• 可以自定义代码存放的地址，这样方便系统的管理。
• 那也就可以实现差分包升级

页数：P533

# Section 5 Operating Modes

页数：P575

# Section 6 Interrupts

描述：中断的介绍在这里啦 引脚的中断、异常的中断都在这里可以看到介绍哦！

当然如果要查某个功能的中断向量表中的中断号：需要在对应模块中的这里找到哦！

# Section 7 sDMA Controller (sDMAC)

大家应该都懂，DMA 嘛，数据搬运。脱离了 CPU 所以不占用 CPU 资源，速度比较快。通过和 CPU 交互去搬运数据。

用到的时候再回来细看吧！

# Section 8 DTS Controller

The Data Transfer Service (DTS) is a DMA controller used to access data without going through the CPU

# Section 9 Reset Controller

页数：P760

描述：复位的控制。包含一些复位的类型以及不同复位不同寄存器的行为

# Reset Categories

页数：P837

描述：这里是详细的复位介绍【小柴就不展开啦】

# Section 10 Power Supply Circuit

页数：P849

# SVR

页数：P865

描述：SVR controller is Synchronous Rectification Step-Down Controller and can directly drive the MOSFET.【同步整流降压控制器】

# Section 11 Power Supply Voltage Monitor

P872

# Delay Monitor

DMON can detect abnormalities in delay time of transistor devices by using an on-chip delay monitor while the microcontroller is working.

总而言之是一些时间上的安全机制

# RAM Retention Voltage Indicator(VLVI)

The very-low-voltage detection circuit (VLVI) is used to detect the RAM retention voltage

大白话就是检测低电压用的，掉电的瞬间可以做一些处理

# Section 12 Temperature Sensor (OTS)

页数：P952

温度传感器【用到的时候再来细看吧！记住它自带温度传感器就好啦】

页数：P969

# 温度传感器测量控制

# Section 13 Clock Controller

页数：P976

The configuration of Main OSC,PLL,and HV IntOSC is variable by Option Byte OPBT10,OPBT11,and OPBT4.

控制：通过设置 OPBT 来控制

# 时钟配置

# 时钟频率设置

# 时钟的具体配置

# Phase Locked Loop(PLL)

页数：P991

# Section 14 Clock Monitor (CLMA)

页数：P1045

# Section 15 Standby Controller (STBC)

页数：P1072

# 芯片待机模式控制

• Types of Chip Standby Mode

  • RUN mode

  • STOP mode

  • DeepSTOP mode

  • Cyclic RUN mode

  • Cyclic STOP mode

# Wake-Up Control

页数：P1075

# 唤醒因子

# I/O Buffer Control

页数：P1080

I/O buffer 在保持状态时 退出深度睡眠模式需要重新配置 port 并设置 IOHOLDn 这个寄存器（具体请见文档）

# Types of Module Standby Mode

# Chip Standby Mode Transition

页数：P1146

描述：介绍了模式转换的处理过程

# Clock Oscillator Behavior During Chip Standby Mode Transition

页数：P1158

描述：介绍了在待机模式中时钟晶振的行为

# Section 16 Low-Power Sampler (LPS)

页数：P1170

低功耗采样器

在不消耗 CPU 资源的情况下监控外部输入（模拟信号 / 数字信号）

# Digital Input Mode

页数：P1189

描述：具体的配置流程用到时再来查吧

# Analog Input Mode

# Section 17 Serial Flash Memory Interface A (SFMA)

The Serial Flash Memory Interface outputs control signals to the serial flash memory connected to the SPI multi I/O bus space, thus enabling direct connection of the serial flash memory.

This module allows the connected serial flash memory to be accessed by directly reading the SPI multi I/O bus space, or using SPI operating mode to transmit and receive data.

通过 SPI 实现串行 flash 内存的直接连接。为了直接连接后地址 mapping 到一块内存。这样在程序中就可以直接访问。

# Operating Modes

页数：P1227

External Address Space Read Mode

• Normal Read Operation (地址是连续的)
• Burst Read Operation（读的地址不是连续的）
• Burst Read Operation with Automatic SPBSSL Negation

# Initial Setting Flow

页数：P1231

# Read Cache

# Transfer Format

页数：P1236

# Section 18 Multi Media Card Interface A (MMCA)

页数：P1245

描述：多媒体卡支持 SD 卡

# Section 19 Multichannel Serial Peripheral Interface (MSPI)

页数：P1292

# Interrupt Requests and Error Notifications

页数：P1294

中断号

# DMA/DTS Trigger

页数：P1302

# 引脚

# 支持的功能

页数：P1310

• Three-wire serial synchronous data transfer
• Master mode and slave mode selectable
• Multiple slaves configuration thanks to up eight configurable chip select output signals
• Maximum transmission speed in master/slave mode
  • In LVDS mode: up to 40 MHz（MSPI0-1）
  • In Single end mode: up to 20MHz（MSPI0-5）,up to 10MHz（MSPI6-9）
• Phase of clock and data selectable for each channel
• Dara transfer with MSB or LSB first selectable for each channel
• Transfer data length selectable from 2 to 128 incremented in 1-bit units for channel
• Three selectable transfer modes:
  • Transmit-only mode
  • Receive-only mode
  • Transmit/receive mode
• Error detection
  • Parity error
  • Data consistency error
  • Over-write error
  • Over-read error
  • Overrun error
• Support of JOB concept for AUTOSAR
• JOB enable control bit for AUTOSAR is provided
• LBM(Loop Back Mode)function for self-test
• Enforced chip select idle setting
• Support Safe-SPI ver1.00 only in master mode
• MSPI has four different interrupt requests
  • Communication status
  • Reception status
  • Communication error
  • Job completion
• MSPI has three DMA requests
  • Communication status
  • Reception status
  • Job completion
• Receive sample point
  • The sample point for the RX can be shifted to the next SCK edge

# DMA

页数：P1315

DMA 中断

DMA 例子

# Basic Operation

页数：P1361

• Master/Slave Mode Operation
• Frame Length and Frame Count
• Chip Select Signal Function
• Clock Polarity and Data Phase
• SOUT Default Level and idle time Level
• Serial Data Direction Selection
• Channel Priority Control
• Error Detection
• Communication Stop or IP initialize
• Loop back mode
• Safe-SPI

# Memory Modes

MSPI 有一个可配置的 RAM 来用作缓冲 buffer

• Direct Memory Mode
• Fixed Buffer Memory Mode
• Fixed FIFO memory Mode

# MSPI 的一些问题和解决办法

页数：P1428

# Section 20 Serial Communication Interface 3 (SCI3)

页数：P1433

串行通信接口可应用于 UART 和 ACIA

# 初始化流程

页数：P1459

# Multi-Processor Communication Function

Using the multi-processor communication function allows data transmission and reception by sharing a communication line between multiple processors by using asynchronous serial communication in which the multi-processor bit is added.

一堆例子

# Section 21 LIN/UART Interface (RLIN3)

接口

中断

页数：P1489

The LIN/UART interface is provided with UART mode and can also be used as a UART.

# 各种模式

• LIN Reset Mode
• LIN Mode
• UART Mode
• LIN Self-Test Mode

# Baud Rate Generator

波特率

页数：P1634

# Noise Filter

噪声过滤

页数：P1637

# Section 22 I2C Bus Interface (RIIC)

页数：P1640

# Functional Overview

• Communications format
  • I2C bus format
  • Master mode or slave mode selectable
  • Automatic securing of the various set-up times, hold times, and bus-free times according to the specified transfer rate.
• Transfer rate
  • Up to 400 kbps
• SCL clock
  • For master operation, the duty cycle of the SCL clock is selectable in the following range: 0% < Duty < 100%
• Issuing and detecting conditions
  • Start, restart, and stop conditions are automatically generated. Start conditions (including restart conditions) and stop conditions are detectable.
• Slave address
  • Up to three slave-address settings can be made.
  • Seven- and ten-bit address formats are supported (along with the use of both at once).
  • General call addresses and device ID addresses are detectable.
• Acknowledgement
  • For transmission, the acknowledge bit is automatically loaded
    • Transfer of the next data for transmission can be automatically suspended on detection of a not-acknowledge bit.
  • For reception, the acknowledge bit is automatically transmitted
    • If a wait between the eighth and ninth clock cycles has been selected, software control of the value in the acknowledge field in response to the received value is possible.
• Wait function
  • In reception, the following periods of waiting can be obtained by holding the clock signal (SCL) at the low level:
    • Waiting between the eighth and ninth clock cycles
    • Waiting between the ninth clock cycle and the first clock cycle of the next transfer (WAIT function)
• SDA output delay function
  • Timing of the output of transmitted data, including the acknowledge bit, can be delayed.
• Arbitration
  • For multi-master operation
    • Operation to synchronize the SCL (clock) signal in cases of conflict with the SCL signal from another master is possible.
    • When issuing the start condition would create a conflict on the bus, loss of arbitration is detected by testing for non-matching between the internal signal for the SDA line and the level on the SDA line.
    • In master operation, loss of arbitration is detected by testing for non-matching of internal and line levels for transmit data.
  • Loss of arbitration due to detection of the start condition while the bus is busy can be detected (to prevent the issuing of double start conditions).
  • Loss of arbitration in transfer of a not-acknowledge bit due to the internal signal for the SDA line and the level on the SDA line not matching can be detected.
  • Loss of arbitration due to non-matching of internal and line levels for data can be detected in slave transmission.
• Timeout function P1723
  • The internal time-out function is capable of detecting long-interval stop of the SCL (clock signal).
• Noise removal
  • The interface incorporates digital noise filters for both the SCL and SDA signals, and the width for noise cancellation by the filters is adjustable by software.
• Interrupt sources
  • Error in transfer or occurrence of events (detection of arbitration loss, NACK, time-out, a start condition including a restart condition, or a stop condition)
  • Reception complete (including matching with a slave address)
  • Transmit-data-empty (including matching with a slave address)
  • Transmission complete

# Interrupt Sources

# Communication Data Format

# Initial Settings

页数：P1687

# Section 23 CANFD Interface (RS-CANFD)

# Interrupt Requests and Error Notifications

# CANFD 配置

页数：P1738

# CAN Mode

# Register behavior in global/channel Modes

页数：P2013

# Initialization

Before joining CAN communications the following shall be configured:

Clock setting

Bit timing setting (nominal and data rate)

Baud Rate setting (nominal and data rate)

CANFD setting

Acceptance Filter setting (configuration of Global Acceptance Filter List)

Reception-, Transmission- and GW-FIFO setting

CAN Communication Mode setting

# Acceptance Filtering Function using Global Acceptance Filter List (AFL)

页数：P2036

描述：过滤配置

# FIFO Buffers & Normal MB Configuration

页数：P2047

描述：Buffer 设置

# Reception and Transmission

页数：P2066

In the RS-CANFD module, CAN messages received on any of the channels, will be stored in RX Message Buffers or in RX FIFO Buffers or Transmit/Receive FIFO Buffers configured in RX Mode or GW Mode depending upon the Acceptance Filter List entries:

Timestamp

# Bus traffic measurement

页数：P2114

# Section 24 FlexRay (FLXA)

页数：P2127

The FlexRay IP-module supports the following features:

特性

页数：P2128

描述：这里可以看到一些涉及到的模块，来了解 FlexRay 的工作机理

# Section 25 Ethernet AVB (ETNB)

页数：P2399

特性

剩下的具体用到再看吧

# Section 26 Single Edge Nibble Transmission (RSENT)

页数：P2667

# Section 27 Peripheral Sensor Interface 5 (PSI5)

页数：P2747

# Section 28 Peripheral Sensor Interface 5 S (PSI5S)

页数：P2814

# Section 29 Renesas High-Speed Serial I/F (RHSIF)

页数：P3029

# Section 30 Clock Extension Peripheral Interface (CXPI)

页数：P3190

# Section 31 Window Watchdog Timer (WDTB)

页数：P3372

# Section 32 OS Timer (OSTM)

页数：P3409

# Section 33 Timer Array Unit D (TAUD)

页数：P3443

The Timer Array Unit D is used to perform various count or timer operations and to output a signal which depends on the result of the operation.

# Section 34 Timer Array Unit J (TAUJ)

页数：P3779

The timer array unit J is used to perform various count or timer operations and to output a signal which depends on the result of the operation.

# Section 35 Motor Control Timer (TSG3)

页数：P3888

# Section 36 Timer Option (TAPA)

页数：P4102

# Section 37 Timer Pattern Buffer (TPBA)

页数：P4125

TPBAn is a 16-bit PWM timer with the duty setting buffer.

# Section 38 Generic Timer Module (GTM)

页数：P4154

# Section 39 Real-Time Clock (RTCA)

页数：P5149

Real-Time Clock (RTCA) has following features:

• Count clock selection from 240 kHz to 2.5 MHz
• Counters for years, months, day of month, day of week, hours, minutes, seconds, and a sub counter. Calendar covers 99 years. Leap years are handled by hardware automatically.
• One Hz pulse output function
• Fixed interval interrupt function
• Alarm interrupt function

时钟：年月日周时分秒

# Section 40 Encoder Timer A (ENCA)

页数：P5197

# Section 41 Peripheral Interconnect (PIC)

页数：P5255

# Section 42 PWM Output/Diagnostic (PWM-Diag)

页数：P5455

This function is comprised of four types of units: clock divider (PWBA), PWM generator (PWGC), A/D conversion trigger select function (PWSD), and A/D converter (ADCJ).

• PWBA
• PWGC
• PWSD
• ADCJ

# Section 43 Analog to Digital Converter (ADCJ)

页数：P5508

# Section 44 Functional Safety

页数：P5726

This section describes the intended safety mechanisms provided to detect the MCU failures with a short detection time. Here, the failures include both the recoverable transient failures such as soft errors of a memory and the unrecoverable permanent failures.

# Section 45 Error Control Module (ECM)

页数：P6265

# Section 46 Data CRC Function K (KCRC)

页数：P6326

# Section 47 Basic Hardware Protection (BHP)

页数：P6344

To protect the code flash memory, data flash memory and Flash extra area, this product has several Flash protection functions.

The security function that is used by the ID authentication and setting of Flash Option Byte is described in this section. The ID code and the Flash Option Byte that is described in this section are mapped at Security Settings area and Block Protection Settings area.

Functional features

• (1) Mode and connection entry protection

• System requires some password base authentication to enter other than Normal operation mode.

• Authentication ID and related option can be configured by Security settings area.

• The 256 bit SPID password authentication is needed to enter Serial programming mode.

• The 256 bit OCDID password authentication is needed when On-chip debug.

• The RHSIF ID authentication is needed to connect to RHSIF Link Partner [For U2A-EVA/U2A16/U2A8 only].

• (2) Flash Protection by ID authentication

• The system requires 256 bit Customer ID authentication for re-programming to User area by each block.

• The Customer ID authentication is needed to read the User/User boot area when debugger is connected.

• The system requires 256 bit Data Flash ID authentication for re-programming to Data area.

• The Data Flash ID authentication is needed to read the Data area when debugger is connected.

• (3) Flash protection by OTP

• User area on code flash supports OTP (One Time Programmable) functionality for each block.

• Flash extra area protection by OTP

• Dedicated configuration area supports OTP functionality for each 4 Byte unit.

• (4) ID code

• Table 47.1* shows the ID code that can be set in this product.

• The system requires each ID authentication for programming and reading the ID.

• Table 47.1 ID Code

• ID Code	Function
  OCD ID	Protection for debug connection
  Serial Programmer ID	Protection to enter the serial programming mode
  RHSIF ID	Protection for RHSIF Link Partner [For U2A-EVA/U2A16/U2A8 only]
  Customer ID A, B, C	Protection for Code Flash and Flash extra area
  Data Flash ID	Protection for Data Flash
  C-TEST ID	Refer to the RH850/U2A-EVA Group Security User’s Manual: Hardware.

• The setting and function that related each ID code can select the Flash Option Byte. The system

• (5) Flash protection by the security function of ICUMHA

• When security function settings by ICUMHA is enabled, programming/erase of the code flash area from masters other than the ICUMHA or Hardware property setting is prohibited. For details, see the RH850/U2A-EVA Group Security User’s Manual: Hardware.

# Section 48 Intelligent Cryptographic Unit/Master (ICUMHA)

页数：P6387

The Intelligent Cryptographic Unit/Master (ICUMHA) is a hardware security module (HSM). ICUMHA can be activated by Option Byte setting

The Intelligent Cryptographic Unit/Master (ICUMHA) is a hardware security module (HSM)

The features of ICUMHA are described below.

• ICUMHA integrates an Intelligent Cryptographic Unit Processor (ICUP) that controls the ICUMHA sub-system and runs the user-defined security services.
• ICUMHA integrates an accelerator that supports a block cipher algorithm based on the AES (Advanced Encryption Standard, FIPS PUB 197).
• ICUMHA integrates several public key cryptographic algorithms like RSA, ECC.
• ICUMHA integrates an accelerator that supports HASH function based on SHA-1, SHA-224 and SHA-256 (Secure Hash Algorithm, FIPS-PUB 180).
• ICUMHA integrates a true random number generator.
• ICUMHA can be used as a slave peripheral to run security services upon request. Also the ICUMHA handles processing of other user-defined security services (for example, checking contents of memory for completeness and integrity) and operates as a master handling procedure to strengthen measures for security.
• ICUMHA has an exclusive read access and programming access to a specific area of non-volatile (flash) memory which contains confidential data (keys and certificates) and highly confidential code for operating security services.

# Section 49 Secure Watchdog Timer (SWDT)

页数：P6391

# Section 50 Debugging and Calibration

页数：P6392

# Section 51 Flash Memory

页数：P6408

Code Flash

• Capacity: Up to 16 Mbytes of User Area and 2x 64 Kbytes of User Boot Area.
• Multi banked configuration.
• Program unit: 512 bytes
• Erase unit: 16 Kbytes for 8 blocks and 64 Kbytes for remaining blocks in each User Area
• OTP (One Time Programmable) is supported for each block.
• Address map swapping between banks is supported

Data Flash

• Data Area:
  • Capacity: Up to 512 Kbytes (Two Data Areas: 256 Kbytes + 256 Kbytes) and 64K bytes for ICUMHA exclusively
  • Program unit: 4, 8, 16, 32, 64, 128 bytes DMA can initiate 4-byte program in multiple time without software overhead. (within one Data Area)
  • Erase unit: Nx 4 Kbytes (N = 1, 2, 3 …) (within one Data Area)
• Hardware Property Area:
  • The settings of this product can be configured in Hardware Property Area in Data Flash Memory. Hardware Property Area consists of Configuration Setting Area, Extended Data Area, Security Setting Area, Block Protection Area, Switch Area, TAG Area and Erase Counter Area.
  • Configuration Setting Area: To store the System Configuration Parameters. (Flash Option Byte, Reset Vector, Software Configuration Option Byte, etc.)
  • Security Setting Area: To store the Security Parameters. (ID Codes, Security Setting flag, etc.)
  • Block Protection Area: To store the Code Flash Protection Settings. (OTP flag, etc.)
  • Switch Area and TAG Area: To update Configuration Setting Area, Security Setting Area and Block Protection Area in an atomic and robust way.
  • Erase Counter Area: To store the Erase Counter.
  • Extended Data Area To store any data to use by user software.Capacity: 2 Kbytes

Other Functions

• Multi FPSYS Operation support
  • The Flash memories that are belonging to the different FPSYS can be programmed/erased simultaneously.

# 51.3.3 Mapping of Hardware Property Area in Data Flash Memory

页数：P6422

# 51.8.4 Switching of Hardware Property Area

页数：P6437

# 51.12 Configuration Setting Area (Option Bytes, Reset Vector)

页数：P6457

# 51.16 Extended Data Area

页数：P6510

用户数据区

# Section 52 RAM

页数：P6532

# Section 53 Boundary Scan

页数：P6535

# Section 54 Package

页数：P6546

封装

# Section 55 Electrical Characteristics

页数：P6553

电气特性

• 55.1 Absolute Maximum Ratings
• 55.2 General & DC Characteristics
  • 55.2.1 Operational Condition
    • 55.2.1.1 Supply Voltage Characteristics
• 55.3 AC Characteristics
• 55.4 A/D Converter Characteristics
• 55.5 Code Flash Characteristics
• 55.6 Data Flash Characteristics
• 55.7 Temperature Sensor Characteristics
• 55.8 Thermal Characteristics
• 55.9 BSCAN Timing

# Section 90 Long-Term System Counter (LTSC)

90.2.1 Functional overview

• 1×64-bit counter
• Free-run up counting
• Atomic read/write access to all registers
• No compare functions
• Clock sources: Peripheral Clock PCLK
• No interrupt functions
• No functions to start/stop multiple counter channels synchronously (Only 1channel)
• Anytime read access to counter registers
• Application reset (SW reset) can be masked. When masked, counter keeps running on reset occurrence and counter register will not be initialized.
• Stop control by Supervisor

The counter register can be read at any time.

# 缘落

当然啦！小柴还是建议大家去看官方手册！！！

这里只是我的一些快速查找知识的笔记。

像那些具体的功能呢用到的时候再去快速的翻到对应的位置。这里就不展开了。毕竟官方手册都 6000 多页啦😫